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“We know a little thing or two because we’ve seen a little thing or two.” -Japan, probably

yep.

And that coincided with the tail end of IMFT - the Intel-Micron NAND joint venture. Intel saw Optane as the new hotness, high-bandwidth X-point NAND that was supposed to be paired with a mechanical SSD; the Windows version of Apple’s Fusion Drive.

It was a flop, much like Intel’s gamble on Rambus RDRAM 20 years ago - and Samsung took the NAND world by storm with their 3D V-NAND.

Wafers are already 3D. It's just that all the dozen or so metal layers are used to route signals and power. Only the critical few layers for the transistors themselves are fabricated using the latest nodes. https://en.wikichip.org/wiki/File:intel_interconnect_10_nm.jpg

I think you might mean GaN which is a different semiconductor material they're using in some power supplies.

GAA stands for gate-all-around and describes the geometry of the transistors (the gate surrounds the channel on all sides, FinFET was just surrounding it on 3 side) not what they're made of

While the actual gate is still in nano?

optomize

gotcha!

Part of the reason the US is forcing companies like TSMC to build a fab in the US is to safeguard against the possibility that China retakes Taiwan, either militarily or politically. What people don't realize is that China doesn't have to physically take TSMC to get the technology. All of China's top semiconductor engineers come from TSMC. (There's also one famous one that defected to Samsung.) That's how China has been able to catch up so fast. This year an American company found that China was already producing a type of 7nm chip, when the industry previously thought it would take them 10-15 years to produce below 10nm.

Taiwan's problem is they are a neo-colony. TSMC is majority foreign-owned. They net between 40-50 billion USD a year. But that money doesn't go to the Taiwanese people. Salaries in Taiwan are notoriously low. The quality of life is maintained by keeping prices artificially low on the island, not by raising incomes. (You can see this in the wide discrepancy between nominal GDP and PPP) So it is relatively easy for the mainland to headhunt top TSMC engineers by offering double or triple what they were making before. Biden, taking a lead from Trump, just passed a series of massively protectionist measures without anybody noticing that would and have raised eyebrows of free-market economists:

https://www.nytimes.com/2022/10/07/business/economy/biden-chip-technology.html

https://carnegieendowment.org/2022/10/27/biden-s-unprecedented-semiconductor-bet-pub-88270

>In addition, the rules require a license for any “U.S. persons”—which include citizens, permanent residents, anyone who lives in the country, and U.S. companies—to work with Chinese companies contributing to advanced semiconductor production in China. All of these groups have been forced to halt work with Chinese semiconductor firms. This has proven immediately damaging, as leading SME firms have had to stop all servicing of equipment at Chinese fabs and many of these machines need maintenance every couple days in order to continue running. In addition, the dearth of experienced U.S. talent will inhibit Chinese industry, since semiconductor fabrication requires the kinds of intangible skills built up over decades of engineering work and can’t be captured in a blueprint or instruction manual. Prior to the new rules announcement, many U.S., Korean, and Taiwanese engineers had responded to this need by taking lucrative positions in the Chinese semiconductor industry—echoing the way Taiwan built up its own chip industry in past decades.

Don't forget Micron's new $15 billion plant in Boise

With a little help

From an old friend

See that's just a marketing name for it, it's actually just a 2D transistor but they draw a little D on there for legality purposes.

> it's now just a name for a fabrication process

Yes and no. The process name is supposed to describe an improvement in transistor density now. As in for the same company, the next node is some % improvement over the previous one. They did this because below 7nm the nm measurement became even more meaningless for indicating transistor size/density.

> has nothing to do with actual values compared to back when it used to

Even when the measurement applied to the smallest "feature size", it still didn't describe the size of the actual transistors or transistor density. For example, Intel 10nm was more transistor dense then TSMC's 7nm process. Intel's 7nm process was targeting a higher density than TSMC's 5nm process. Intel fell behind TSMC because they tried to do it on DUV machines rather than EUV, which set them back years as TSMC wound up getting access to EUV equipment first. Hell, even with 7nm, TSMC's was better than Samsung's equivalent process.

They're not starting from scratch. IBM demonstrated their 2nm process over a year and a half ago, they were the first to do so. They're at the stage where they're getting it from the lab to production.

IBM's not a newcomer to the fab business, they've just been mostly focused on producing their own chips for their own enterprise/datacenter equipment rather than mass market equipment. I'm betting that this partnership is IBM eyeing the fab-only business model; or looking to get themselves fabless like how AMD divested themselves of their fabs and spun off Global Foundries.

Neither. China has 0 access to the equipment that fabs leading node chips. People don't seem to understand that there's the fab process and then there's the fab equipment. TSMC, Samsung, and Intel all buy the same fab equipment from the same manufacturers, they don't make their own. All of those companies are from the US, the EU, and Japan. And it's impossible for them to keep these machines working without the expertise and replacement parts from the equipment manufacturers.

If China ever goes to war with Taiwan, they lose access to the entire semiconductor supply chain. Not to mention they also lose access to silicon wafer producers who are almost entirely US and Japan based.

Yall remember when IBM provided technology to the Third Reich that allowed Nazis to persecute and kill Holocaust victims more efficiently??? Well Pepperidge farms remembers

Tbf Japan does have some form on the "attempting to take over things" front

Optimistic__Elephant lands on the moon with a little help from Neil Armstrong.

chinese chip manufacturers hate this one trick…

Also how you end up with nonsense like this.

picometers

Completely refitting fab 9.

TBF to angstrom that is the length of atomic bonds so it’s a lot easier to say a carbon atom is a little over an angstrom than 130 pm

Agreed on most other non-standard measurements though

It’s true. I work for ASML and things keep getting smaller

PSA: ISA =/= implementation.

While it was common to suggest in the late 90s and early 2000s that there was a strong distinction between CISC and RISC styles of architecture, owing to CISC having a wide variety of purpose built instructions that aided in accomplishing specific tasks quickly, while RISC would have fewer transistors sitting around doing nothing (idle transistors do still consume some power, btw) as a consequence of bloated instruction sets, in reality, modern ISAs have a mix of CISC and RISC philosophies built in, and more important than a core being ARM or x86, is the way that core is implemented.

In reality, if you look at a variety of implementations of ARM cores, there actually isn't as big an efficiency improvement gen over gen as you would expect, as seen in the Snapdragon 865, 870, 888, and 8 gen 1 all performing relatively closely in longer tasks (though they do benchmark quite differently in benchmarks that test a series of tasks in very short bursts), and actually not being that out of line with certain x86 chips, such as something like a 5800X3D (were one to extrapolate its performance when compared to a 5800X power limited to similar wattage to the SD SoCs), or say, a Ryzen 6800U processor power limited to 5W.

​

That's not to say that there isn't ARM IP out there that can be beneficial to improving performance at lower power draw, but I'd just like to highlight that a lot of the improvements you see in Apple Silicon aren't necessarily down to it being ARM, but due to it being highly custom, and due to Apple having varying degrees of control over A) the hardware, B) the drivers / OS / software stack, and C) the actual apps themselves. If you're able to optomize your CPU architecture for specific APIs, programming languages, use cases, and operating systems, there's a lot of unique levers you can pull as a whole ecosystem, as opposed to say, just a platform agnostic CPU vendor.

Another thing to note is that while Apple saw a very respectable increase when jumping from Intel to their in house M1 chips, it's not entirely a fair comparison between x86 and ARM as instruction sets, as the Intel implementation was implemented on a fairly inferior node (14 nanometer IIRC), while the M1 series was implemented on a 5nm family node, or possibly more advanced. When taking this into account, and comparing the Intel versus M1 macs, you may want to remove anywhere between 80 to 120% of the performance per watt improvements to get a rough idea of the expected impact of the node, with what's left being a combination of the various ecosystem controls Apple has available.

When compared to carefully undervolted Raptor Lake chips, or equally carefully managed Zen 4 processors, the Apple SoCs, while respectable in what they do (and being respectable as a result of many things not owing to their ARM ISA), they aren't alien tech or anything; they're simply a well designed chip.